The present invention relates generally to the field of phase locked loops, and more specifically to a lock detection circuit using a cycle slip detector with clock presence detection, permitting a large variation of the clock phase or frequency and adequate time for the PLL to react to the disturbance without causing false alarms, while providing an alarm to PLL behavior consistent with a significant deviation from the lock condition in a small, low power and low noise digital solution.
The phase lock loop (PLL) is commonly used in digital circuitry to provide precise phase and frequency locking and synchronization of clock signals. Applications include, for example, anything requiring clock synchronization or clock synthesis, such as data transmission and telecommunications.
FIG. 1 illustrates a typical PLL circuit of a prior art. The PLL 100 of FIG. 1 includes a phase/frequency detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) a buffer inverter 150 for the VCO output PLL_OUT, and a frequency divider 160. The phase/frequency detector 110 compares the phase and frequency of an input reference clock signal REF_CLK with those of a feedback signal FB_VCO and in response generates phase/frequency correction signals for the charge pump 120. The phase/frequency correction signals comprise an Up signal and a Down signal transmitted on two separate signal paths. The Up and Down signals depend upon the relationship of the phase of the feedback signal FB_VCO to the input clock signal REF_CLK. For example, when the input clock signal REF_CLK and the feedback signal FB_VCO are in a perfect phase lock, the Up and Down signals generated by the phase/frequency detector 110 have perfectly matched pulses with an equal pulse width, as shown in FIG. 2A.
FIG. 2B shows the pulses of the up and down signals when an up shifting of the phase locked loop output signal PLL_OUT is required to enable the feedback signal FB_VCO to be phase locked with the input clock signal REF_CLK. In this case, the pulse width of the up signal is greater than that of the down signal. Only the leading edges of the corresponding pulses of the up an down signal are timed to coincide with each other, whereas the trailing edges of the up signal pulses lag behind those of the corresponding down signals pulses and vary with the timing difference between the clocks input to the phase/frequency detector 110.
FIG. 2C shows the pulses of the up and down signals when a downshifting of the phase locked loop output signal PLL_OUT is required to enable the feedback signal FB_VCO to be phase locked with the input clock signal REF_CLK. In this situation, the pulse width of the down signal is greater than that of the up signal. Here, only the trailing edges of the corresponding pulses of the up an down signal are timed to coincide with each other, whereas the leading edges of the down signal pulses lead ahead those of the corresponding up signals pulses and vary with the timing difference between the clocks input to the phase/frequency detector 110.
Referring back to FIG. 1, the charge pump 120 generates a pump current IC in response to receiving the up and down signals from the phase/frequency detector 110. The charge pump 120 detects a difference between the pulse width of the up and down signals generated by the phase/frequency detector 110 and adjusts the pump current IC if the pulses of the up and down signals do not match each other. For example, when the input clock signal REF_CLK and feedback signal FB_VCO are in a perfect phase lock and the up and down signal pulses are perfectly matched as shown in FIG. 2A, no phase or frequency shift in the output signal PLL_OUT is required, and therefore no change in the pump current IC is required.
In the case in which the phase/frequency detector 110 outputs up and down signal pulses as shown in FIG. 2B, the charge pump 120 determines that the pulse width of the up signal is greater than that of the down signal and in response adjusts the pump current IC upward to increase the frequency FHI of the output signal PLL_OUT, such that the frequency of the feedback signal FB_VCO is increased to achieve a phase lock with the input clock signal REF_CLK. In the case in which the phase/frequency detector 110 outputs up and down signal pulses as shown in FIG. 2C, the charge pump 120 determines that the pulse width of the down signal is greater than that of the up signal and in response adjust the pump current IC downward to decrease the frequency of the output signal PLL_OUT in order to achieve a phase lock between the signals REF_CLK and FB_VCO.
In this way, the conventional PLL is able to react to a limited phase difference between the input reference clock and the feedback VCO clock in order to regain frequency lock. Generally, for example, this allowable phase difference is less than 360 degrees.
The loop filter 130 in FIG. 1 may be either a conventional passive loop filter or a conventional active loop filter which filters out undesirable noises and high frequency jitters in the pump current signal IC generated by the charge pump 120.
The loop filter 130 outputs a control voltage VC to the VCO 140, which in response generates a phase locked loop output signal PLL_OUT having a typically high output frequency FHI. The output frequency FHI generated by the VCO 140 is dependent upon the control voltage VC. In a PLL feedback loop, the conventional PLL 100 may include a frequency divider 160 which divides the output frequency FHI of the PLL by a predetermined divisor M, to generate the feedback signal FB_VCO, which is typically divided down to a lower frequency FLO. The divisor M, that is, the ratio of the frequency FHI of the PLL output signal PLL_OUT to the frequency FLO of the feedback signal FB_VCO, is determined by the desired frequency FHI of the output signal PLL_OUT relative to the frequency of the input clock signal REF_CLK.
When the input clock signal REF_CLK is initially provided to the phase/frequency detector 110 in the conventional PLL as shown in FIG. 1, the control voltage VC from the loop filter 130 may take a finite time before it settles to a steady-state voltage level to achieve a phase lock. FIG. 3 illustrates a typical curve of the loop filter control voltage vs. time (VC vs. t) 180, which shows the magnitude of the loop filter control voltage VC from the time of starting the input clock signal REF_CLK at VCI (initial control voltage) to the time of achieving a steady-state voltage VCF (final control voltage) at point C. Prior to the steady-state point C, the loop filter control voltage VC, which controls the frequency FHI of the PLL output signal PLL_OUT, may overshoot A and undershoot B again due to relatively large variations in the up and down signals from the phase/frequency detector 110 shortly after the phase locking operation is initiated. In addition, the initial control voltage VCI corresponds to an initial VCO starting frequency which may be very low. Therefore, the time required tLOCK, for the PLL to achieve lock after the REF_CLK signal is initially applied, may involve a substantial delay.
Additionally, during a transient state prior to achieving the steady state frequency, the control voltage VC may cause the conventional PLL as shown in FIG. 1 to achieve a xe2x80x9cfalse phase lockxe2x80x9d condition as VC crosses the final control voltage set point VCF, yet is still in a transient state until the voltage level of VC stabilizes in correspondence with the feedback.
In order to avoid data errors which may occur due to a false lock from a PLL, prior art using fixed time delays have been provided after the clock start. However, a fixed time delay does not ensure a true phase lock because the duration of the transient state prior to achieving the steady state will not be the same for each phase locking operation because of the nonlinear nature of locking. A very long delay to assure that false locks do not occur is also undesirable due to fast circuit start up time requirements for many circuits.
PLL 100 further includes a lock detector 170 which also uses the input clocks REF_CLK and FB_CLK. The lock detector 170 determines whether input clock signals are in phase or out-of-phase (not locked), and may provide a visible indication of the condition to a user.
Many conventional PLL systems also use a lock detector circuit to do a system reset. A reset, however, is a disastrous change to the operation of most systems. In a PLL, a reset can start the loop operating at a very low frequency (as indicated by VCI in FIG. 1, or even no output) and then acquiring lock at the normally much higher output operating frequency. Consequently, a small phase shift in a PLL that would marginally effect the system can cause a huge disruption in the operation of the system from a reset. Normal operations of a PLL can respond to a disturbance in a manner that makes it appear defective.
Quadrature phase detector, time window edge comparison, tune voltage window comparator, and cycle slip detection are the most common methods for lock detection. A tune voltage window comparator would significantly reduce the output frequency range because of the variation of voltage trip points with process, temperature, and voltage.
Except for the tune voltage window comparator, these lock detection schemes require the presence of the reference and divided down VCO clocks. A loss of one of the clocks causes the PLL to give a false alarm.
Accordingly, there is a need for a lock detection circuit of a phase locked loop which permits a large variation of the clock phase or frequency and adequate time for the PLL to react to the disturbance without causing false alarms, while providing an alarm to PLL behavior consistent with a significant deviation from the lock condition in a small, low power and low noise digital solution.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a lock detection circuit of a phase locked loop used in a communications device. The purpose of the lock detection circuit according to an exemplary aspect of the present invention, is to alarm on behavior that shows the PLL has had a significant deviation from the lock condition. Conventional operations of a PLL can respond to a disturbance in a manner that makes it appear defective. Consequently, the best lock detection schemes will allow some time for the loop to respond to a disturbance and recover. In this way, a system reset or the false alarms previously discussed may be avoided.
To accomplish this, the lock detection circuit of the present invention includes a cycle slip detector and a clock presence detector. With the innovative use and combination of these detector circuits, the present invention intends to redefine the PLL from a simple phase (e.g., typically  less than 90 degrees) locking device, to one which includes multiple cycles (e.g., 16 cycles of 360 degrees each) and frequency locking capabilities.
In the process of this redefining, some terms will also be defined. The lock detection circuit, according to the present invention, continuously monitors the reference clock, the feedback VCO clock, and determines the phase and cycle (360 degrees) count difference between these clocks following the last point of phase lock (when the clocks were at the same frequency and phase). The lock detection circuit determines the total phase and cycle difference between the reference clock and the feedback VCO clock signals;
xe2x80x83360 degrees phase difference=1 cycle slip
in terms of reference clock counts since the last cycle slip. This reference clock count is then, at the desired PLL lock frequency, also a measure of the total elapsed time since the last cycle slip. A 4 bit counter, for example, within the lock detection circuit is coupled to the output of the cycle slip detector to store the reference clock count (e.g., 16 counts maximum for a 4 bit counter). After a cycle slip occurs, the counter resets to a count of 0, and outputs a CYCLE SLIP alarm indication for the PLL. On the other hand, if the PLL does regain lock without a cycle slip, the reference clock counter will continue counting up until the maximum count is attained. At the maximum count, the counter latches and indicates a NO CYCLE SLIPS state indication. In this way, the counter allows time for the PLL to recover from a disturbance without producing false alarm indications, or a PLL reset.
Thus, the cycle slip detector receives a reference clock and a VCO feedback clock, and in response to the frequency difference between the reference clock and the VCO feedback clock that remains for a time period greater than the inverse of the frequency difference of the clocks, generates a cycle slips alarm indication. The cycle slips alarm status enables the lock detection circuit to provide an indication to the PLL, of the lock condition and whether a cycle slip has occurred. The phase difference may be detected, for example, by a phase/frequency detector.
In operation, the cycle slip detector uses a phase/frequency detector which in response to the frequency difference between the reference clock and the VCO feedback clock, generates UP pulses and DOWN pulses, which are coupled into an UP cycle slip detector and a DOWN cycle slip detector respectively. The UP and DOWN cycle slip detectors respond to the beat frequency of the difference between the clocks to produce a pulse when the pulse width of the frequency difference xe2x80x9crolls overxe2x80x9d from its largest pulse width to its narrowest pulse width. This roll over occurs with each cycle slip, providing a new cycle slip detection.
A logical AND of the UP and DOWN cycle slips, produces a cycle slip detection which is independent of the clock with the higher frequency. The output of the cycle slip detector, is a cycle slip detection pulse which triggers, for example, a 4 bit counter to track the time since the last cycle slip detection, in terms of reference clock counts up to a maximum of 16 reference clock cycles. In this way, adequate time (e.g., 16 reference clocks) is allowed for the PLL to respond to a disturbance without false alarm indications, or a PLL reset.
The cycle slip detector requires the presence of both the reference clock and the divided down VCO clock (feedback VCO clock), but does not detect the loss of either of these input clocks. With one clock missing, the output of the cycle slip detector stays a constant high, which indicates a locked condition to the following circuitry. In a conventional PLL circuit, for example, the momentary loss of either one of the clock signals gives a false alarm indication. A clock presence detector is therefore provided in the present invention to avoid these false alarms.
While the cycle slip detector continuously monitors the phase difference between the reference clock and the feedback VCO clock for a predetermined elapsed time, the clock presence detector, according to the present invention, continuously monitors for a loss of one of the clocks for a predetermined elapsed time. Advantageously, clock presence may also be detected, for example, by the use of the same, or another phase/frequency detector, thereby providing a commonality of circuitry and/or the usage of fewer components.
Once the clock presence detector has detected the loss of a clock signal, the other remaining clock (reference clock, or feedback VCO clock) is counted in, for example, another 4 bit counter. This remaining clock count is then, at the desired PLL lock frequency, also a rough measure of the total elapsed time that the clock has been missing. Therefore, the remaining clock count (e.g., 16 clock cycles for a 4 bit counter) allows for a predetermined correspondence to time for the missing clock to return without false alarm indications, or a PLL reset.
In the event of a catastrophic failure, where both clocks are missing, the result is unknown.
The clock presence detector receives the reference clock and the VCO feedback clock, and in response to determining whether the reference clock or the VCO feedback clock is missing for a time greater than a predetermined count of either remaining clock, generate a no VCO alarm and/or a no REF alarm indication. The no VCO alarm and the no REF alarm enables the lock detection circuit to provide an alarm indication to the PLL of the presence of the reference clock and the VCO feedback clock.
Conventional solutions for the loss of a clock signal would require a significantly larger number of counters for the same accuracy and in addition, need a third reference clock. This third reference clock could inject a signal to the PLL and cause jitter at the output.
Quadrature phase detection, time window edge comparison, tune voltage window comparison, and frequency discrimination are the most common methods for lock detection. Of these, quadrature phase detection, tune voltage window comparison, and frequency discrimination require a significant amount of analog circuitry which would require more chip area and power than the digital solution presented. The tune voltage window comparison detector may generate a number of false alarms because of variations in the phase error of the PLL as the loop corrects for various disturbances.
Thus the innovative lock detector of a phase locked loop permits a large variation of the clock phase or frequency and adequate time for the PLL to react to the disturbance without causing false alarms, while providing an alarm to PLL behavior consistent with a significant deviation from the lock condition, in a small low power and low noise digital solution.
In accordance with the present invention, a lock detector for a phase locked loop is disclosed. The innovative lock detector incorporates the use and combination of a cycle slip detector and a clock presence detector into the present invention, which attempts to redefine the PLL from a simple phase locking device, to one with frequency locking capabilities. The lock detector permits multiple cycles of phase disturbance to be tolerated, without false alarm indications. In addition, the lock detector permits a temporary loss of multiple cycles of a clock to be tolerated, without false alarm indications.
In one exemplary aspect of the invention, both the cycle slip detector and the clock presence detector utilize a phase/frequency detector to monitor the phase and cycle difference between the reference clock and the feedback VCO clock. Thus, a feature of the present invention is that the same phase/frequency detector may be used for each detector as well as the PLL, to provide a commonality of circuitry, minimize the amount of hardware, and the number of spurious signals. In addition, an extra third clock is unnecessary, which minimizes noise coupling to the loop.
An exemplary feature of the circuit of this invention, therefore, provides an all digital solution to provide a technique which has a higher noise immunity than a conventional method.
Additionally, the cycle slip detector of the present invention, allows 360 degrees of phase shift before detecting a cycle slip, which allows enough time for the PLL to react to disturbances without causing a false alarm.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.